基于bp反投影成像算法的硬件加速器以及数据处理方法

Hardware accelerator based on BP back-projection imaging algorithm and data processing method

Abstract

The invention relates to a hardware accelerator based on a BP back-projection imaging algorithm. The hardware accelerator comprises a pulse storage used for storing a large amount of pulse data, an image data storage module which comprising at least two continuous image data storages used for storing source data and result data around every back-projection operation, a back-projection operation unit used for conducting back-projection operation to achieve a delaying adjusting and coherent accumulation function and an AHB connector used for integrating the pulse storages, the image data storages and the back-projection operation units to finish information interaction among the pulse storages, the image data storages and the AHB bus. The hardware accelerator has the advantages of adopting fixed points with proper bit wide to replace double-accuracy floating points commonly used to conduct calculation, operation errors and logic resource use are reduced, and phase error is reduced from 11.25 degrees to 1.4 degree. A back-projection imaging data processing method is provided to achieve seamless joint of assembly lines, the high data throughput rate is obtained, and the parallelization of algorithm is effectively achieved.
本发明涉及一种基于BP反投影成像算法的硬件加速器,包括脉冲存储器,用于存储大量的脉冲数据;图像数据存储模块,包括至少两个连续的图像数据存储器,用于存储每次反投影运算前后的源数据和结果数据;反向投影运算单元,用于进行反投影运算,实现时延调整和相干累加功能;以及AHB接口,用于集成所述脉冲存储器、图像数据存储器以及反向投影运算单元,完成三者与AHB总线之间的信息交互。有益效果为:1)采用合适位宽的定点数代替一般使用的双精度浮点数来进行计算,这样做减小了运算误差以及逻辑资源的使用。其相位误差由11.25°减小到1.4°。(2)提出了反投影成像数据处理方法,实现各级流水线无缝对接,获得较高的数据吞吐率,有效实现算法的并行化。

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